1. Field of the Invention
The present invention relates to semiconductor devices, particularly to a configuration for reducing a current consumption of a semiconductor device including a logic gate constituted by CMOS transistors (complementary insulated gate type field effect transistors). More specifically, the invention relates to a configuration for reducing a subthreshold current of a semiconductor memory device such as a DRAM (dynamic random access memory).
2. Description of the Background Art
A CMOS circuit is known well as a semiconductor circuit with a quite small power consumption.
FIG. 24 is a diagram showing configuration of a CMOS inverter. In FIG. 24, the CMOS inverter includes a p-channel MOS transistor (insulated gate type field effect transistor) PT connected between a power source node 900 receiving one operation power source voltage Vcc and an output node and receiving an input signal IN at its gate, and an n-channel MOS transistor NT connected between another power source node 902 receiving another operation power source voltage Vss (usually the ground potential) and the output node 901 and receiving the input signal IN at its gate. A load capacitor C exists at the output node 901. When the input signal IN is at a low level, the p-channel MOS transistor PT is turned on and the n-channel MOS transistor NT is turned off, and the load capacitor C is charged through the p-channel MOS transistor PT and an output signal OUT attains the level of the power source voltage Vcc. When the charging of the load capacitor C is finished, the p-channel MOS transistor PT is turned off since its source and drain attain the same potential. Consequently, no current flows in this state and the power consumption can be neglected.
When the input signal IN is at a high level, the p-channel MOS transistor PT is turned off and the n-channel MOS transistor NT is turned on, and the load capacitor C is discharged through the n-channel MOS transistor NT and the potential at the output node 901 becomes the level of the other power source potential Vss. When the discharging is finished, the n-channel MOS transistor NT is turned off since its source and drain attain the same potential. Consequently, the power consumption power can be neglected in this state too.
A drain current IL flowing through a MOS transistor is expressed by a function of the gate-source voltage of the MOS transistor. If the absolute value of the gate-source voltage becomes larger than that of the threshold voltage of the MOS transistor, a large drain current will flow. Even if the absolute value of the gate-source voltage becomes equal to or less than the absolute value of the threshold voltage, the drain current does not completely become 0. The drain current flowing in this voltage region is called a subthreshold current and is exponentially proportional to the gate-source voltage.
FIG. 25 shows subthreshold current characteristics of an n-channel MOS transistor. In FIG. 25, the abscissa shows a gate-source voltage VGS, and the ordinate shows the logarithmic value of a drain current IL. In FIG. 25, current IL in straight line region of curves I and II is the subthreshold current. The threshold voltage is defined as a gate-source voltage causing a prescribed current flow in the subthreshold current region. For example, a gate-source voltage causing a drain current of 10 mA flowing in a MOS transistor with gate width (channel width) of 10 .mu.m is defined as the threshold voltage. In FIG. 25, the threshold voltages VT0 and VT1 corresponding to the prescribed current I0 are shown.
With miniaturization of a MOS transistor, the power source voltage Vcc is also lowered according to the scaling rule. Therefore, the absolute value of the threshold voltage Vth of the MOS transistor must be lowered also according to the scaling rule in order to improve the performance. For example, in the CMOS inverter shown in FIG. 24, provided that the power source voltage Vcc is 5 V and the threshold voltage Vth of the n-channel MOS transistor NT is 1 V, when the input signal IN changes from 0 V to 1 V or more, a large drain current is caused and discharging of the load capacitor C begins. When the threshold voltage Vth remains the same value and the power source voltage Vcc is lowered to 3 V for example, unless the input signal IN becomes 1 V or more, the n-channel MOS transistor NT cannot be turned on and the load capacitor C cannot be discharged by a large current. That is, when the power source voltage Vcc is 5 V, discharging of the load capacitor is started at the time of 1/5 of the amplitude of the input signal IN, whereas when the power source voltage Vcc is 3 V, discharging of the load capacitor C begins at the time of 1/3 of the amplitude of the input signal IN. Consequently, the input/output response characteristics are deteriorated and the high speed operation cannot be assured. Therefore the absolute value of the threshold voltage Vth must be scaled in a similar manner to the power source voltage.
However, as shown in FIG. 25, if the threshold voltage VT1 is lowered to the threshold voltage VT0, the subthreshold current characteristics are moved from the curve I to the curve II. In this case, since the subthreshold current when the gate voltage becomes 0 V (Vss level) increases from IL1 to IL0 and the current consumption increases, the absolute value of the threshold voltage Vth cannot be scaled down in a similar manner to the power source voltage, and implementation of excellent operation characteristics, particularly high speed operation characteristics, becomes difficult.
A configuration to suppress a subthreshold current without deteriorating the high speed characteristics is disclosed in 1993 Symposium on VLSI Circuit Digest of Technical Papers, pp. 47-48 and pp. 83-84 by Horiuchi et al. and Takashima et al. respectively.
FIG. 26 is a diagram showing the configuration of a power source line disclosed by Horiuchi et al. in the above-mentioned reference. In FIG. 26, n CMOS inverters f1-fn in cascade connection exemplify a CMOS circuit. Each of the inverters f1-fn has the same configuration as that shown in FIG. 24.
In the path where one operation power source voltage is supplied, a first power source line 911 is connected to a first power source node 910 receiving the power source voltage Vcc, and a second power source line 912 is arranged in parallel to the first power source line 911. The first power source line 911 and the second power source line 912 are connected through a high resistor Ra of a high resistance. In parallel to the resistor Ra, a p-channel MOS transistor Q1 is arranged for connecting the first power source line 911 and the second power source line 912 selectively in response to a control signal .phi.c. A capacitor Ca having relatively large capacitance to stabilize the potential of the second power source line 912 is also arranged between the first power source line 911 and the second power source line 912.
The transmission path of another power source voltage Vss (ground potential: 0 V) includes a third power source line 921 connected to a second power source node 920 receiving the other power source voltage (hereinafter referred to simply as "ground voltage") Vss, and a fourth power source line 922 arranged in parallel to the third power source line 921. A high resistance resistor Rb is provided between the third power source line 921 and the fourth power source line 922, and in parallel to the resistor Rb is arranged an n-channel MOS transistor Q2 connecting the third power source line 921 and the fourth power source line 922 selectively in response to a control signal .phi.s. A capacitor Cb having large capacitance to stabilize the potential of the fourth power source line 922 is also arranged between the third power source line 921 and the fourth power source line 922.
Each of the inverters f1, f3 . . . in odd stages has one operation power source node (power source node receiving a high potential) connected to the first power source line 911, and other power source node (power source node receiving a low potential) connected to the fourth power source line 922. Each of the inverters f2, . . . in even stages has one operation power source node connected to the second power source line 912, and other power source node connected to the third power source line 921. Now, operation will be described.
In a DRAM, the state of a signal at the standby state can be predicted previously. Also the state of an output signal can be predicted. In the configuration shown in FIG. 26, the input signal IN becomes low level in the standby state and becomes high level in the active cycle. In the standby cycle, the control signal .phi.c is at high level and the control signal .phi.s is at low level, and both transistors Q1 and Q2 are turned off. In this state, the power source lines 911 and 912 are connected through the resistor Ra, and also the power source lines 921 and 922 are connected through the resistor Rb. The potential VCL of the power source line 912 becomes EQU VCL=Vcc-Ia.multidot.Ra
and the potential VCL of the power source line 922 becomes EQU VSL=Vss+Ib.multidot.Rb
where Ia and Ib designate currents flowing through the resistors Ra and Rb respectively. Now, the input signal IN is at the level of ground potential Vss. In the inverter f1, the p-channel MOS transistor PT is at the ON-state and the output node is charged to the level of power source potential Vcc on the power source line 911. On the other hand, in the n-channel MOS transistor NT, its source potential (potential of the power source node 902) is the intermediate potential VSL and is set to the potential level higher than the ground potential Vss. Consequently in the n-channel MOS transistor NT, its gate-source voltage becomes a negative voltage. As shown in FIG. 25, when the gate-source voltage is -VSL, the subthreshold current becomes the subthreshold current IL2, which is smaller than the subthreshold current IL1 flowing when the potential of the power source node 902 is the ground potential Vss. Here, the operation characteristics of the MOS transistor will be described according to the curve I shown in FIG. 25. As to the ON/OFF state of the n-channel MOS transistor, the state is referred to as the ON-state where the gate-source voltage is higher than the threshold voltage, and the state is referred to as the OFF-state where the gate-source voltage is lower than the threshold voltage. Reversed relationship applies to the case of the p-channel MOS transistor.
In the inverter f2, the input signal /IN (output signal of inverter f1) is at the high level of the power source potential Vcc. In the inverter f2, the p-channel MOS transistor is turned off and the n-channel MOS transistor is turned on. In the p-channel MOS transistor, its source is connected to the power source line 912 and receives the voltage VCL. The gate potential of the p-channel MOS transistor becomes higher than the source potential in the inverter f2, and also the subthreshold current is suppressed in similar manner to the case of the n-channel MOS transistor. The above-mentioned relation applies also to the inverters f3-fn at subsequent stages. Consequently, in the standby state, the subthreshold current in the inverters f1-fn is suppressed and the standby current is reduced.
When the active cycle begins, the control signal .phi.c is made low in level and the control signal .phi.s is made high in level, and both MOS transistors Q1 and Q2 are turned on. The-MOS transistors Q1 and Q2 each have a large channel width W and can supply charge/discharge currents sufficiently to the inverters f1-fn. In this state, the potentials of power source lines 912 and 922 attains the levels of power source potential Vcc and the ground potential Vcc respectively. Thereby, in the active cycle, according to the input signal IN, the output signal OUT is brought to the determined state.
FIG. 27 shows operation waveforms and current flowing through the power source line in the circuit shown in FIG. 26. As shown in FIG. 27, at the standby cycle, in response to the signals .phi.s and .phi.c, both MOS transistors Q1 and Q2 are turned off, and the voltage VCL on the power source line 912 and the voltage VSL on the power source line 922 each attain the intermediate potentials between the power source potential Vcc and the ground potential Vss (0 V) respectively. In this state, in the inverters f1-fn, the MOS transistor in the subthreshold region (MOS transistor in the OFF-state) is at more strong OFF-state and the subthreshold current is reduced.
At the active cycle, the control signals .phi.s and .phi.c are made high and low respectively, and the MOS transistors Q1 and Q2 are turned on, and the voltage VCL on the power source line 912 becomes equal to the power source potential Vcc and the voltage VSL on the power source line 922 becomes equal to the ground potential Vss. At the start of the active cycle, the power source current Icc (VCL charging current) flows in order to charge the power source line 912, subsequently when the input signal IN is changed, the inverters f1-fn are operated in response to this change, and charge/discharge currents are produced in order to change the signal levels and a relatively large operation current is produced.
At the transition from the standby cycle to the active cycle, the transistors Q1 and Q2 are turned on and the voltages VCL and VSL are made equal to the power source potential Vcc and the ground potential Vss respectively. The power source lines 912 and 922 are accompanied by interconnection line capacitance or parasitic capacitance by the transistor connected thereto (junction capacitance of a transistor), and some time period is required until the voltages VCL and VSL of the power source lines 912 and 922 are restored to the power source potential Vcc and the ground potential Vss respectively. When the difference between voltage VCL and power source potential Vcc and the difference between the voltage VSL and the ground potential Vss are enlarged in order to decrease the standby current, a long time is required until the voltages VCL and VSL of the power source lines 912 and 922 are restored to the prescribed potentials Vcc and Vss respectively. When circuits (inverters f1-fn) connected to the power source lines 912 and 922 are operated, the voltage level of these main power source lines becomes unstable and the operation speed of these circuits becomes slow (in general, the operation speed of a MOS transistor is given as a function of its gate voltage and the power source voltage.), and the operation characteristics to satisfy the required condition cannot be obtained and the delay of signal propagation becomes large. Therefore, a circuit receiving the operation power source voltages from the power source lines 912 and 922 must start the operation after the voltages VCL and VSL of the power source lines 921 and 922 are restored to the power source potential Vcc and the ground potential Vss. Thus, a problem arises that the operation start timing of a circuit connected to the power source lines 912 and 922 becomes late, and in the case of the DRAM, the access time becomes long.